1. Field of the Invention
The present invention relates to methods of fabricating a semiconductor device and, more particularly, to methods of fabricating a semiconductor device including a metal oxide semiconductor (MOS) transistor with a strained channel.
2. Description of Related Art
MOS transistors are widely employed as switching devices of semiconductor devices. Accordingly, fabrication of high performance MOS transistors is required in order to improve characteristics of the semiconductor devices. A salicide technique is widely used in fabrication of the high performance MOS transistors.
According to the salicide technique, a metal silicide layer is selectively formed on a gate electrode and source/drain region of a MOS transistor. Thus, it can substantially reduce electrical resistivity of the gate electrode and source/drain regions. A cobalt silicide layer or a titanium silicide layer is widely used as the metal silicide layer. In particular, the cobalt silicide layer exhibits low dependence of resistivity on its line width. Accordingly, the cobalt silicide layer has been widely used in fabrication of a gate electrode of a short channel MOS transistor. However, in the event that the gate electrode has a narrow width less than about 0.1 μm, there is a limitation in applying the cobalt silicide layer to the gate electrode because of the phenomenon called “agglomeration”. Thus, recently, a nickel salicide technique is widely used in fabrication of high performance MOS transistors.
A nickel silicide layer formed using the nickel salicide technique may have various composition ratios. For example, the nickel silicide layer may be a di-nickel mono-silicide (Ni2Si) layer, a mono-nickel mono-silicide (NiSi) layer, or a mono-nickel di-silicide (NiSi2) layer. The mono-nickel mono-silicide (NiSi) layer has the lowest resistivity out of the various nickel silicide layers. The mono-nickel mono-silicide layer is formed at a low temperature of 350–550° C., whereas the mono-nickel di-silicide layer is formed at a higher temperature than 550° C. Accordingly, the nickel silicide layer should be formed at a low temperature below 550° C. to have a low resistivity.
There is an alternative approach to achieve the high performance MOS transistors. That is, a method of forming a strained channel has been proposed in order to improve performance of the MOS transistors. The strained channel has a greater lattice constant than silicon. Accordingly, mobility of carriers in the strained channel is increased, thereby improving a switching speed of the MOS transistor. The methods of forming the strained channel are taught in U.S. Pat. Nos. 6,358,806 B1 and 5,683,934. According to the U.S. Pat. Nos. 6,358,806 B1 and 5,683,934, the strained channel is formed using a silicon carbide layer and/or an epitaxial growing technique. However, highly precise, accurate and complicated processes are required in order to employ the silicon carbide layer and the epitaxial growing technique.
In the meantime, methods of forming a borderless contact are taught in U.S. Pat. No. 6,265,271 B1 to Thei et al. According to Thei et al., an etch stop layer is formed on an entire surface of a semiconductor substrate having a MOS transistor fabricated using a salicide technique. The substrate having the etch stop layer is annealed to densify the etch stop layer. The annealing process is performed at a temperature within the range of 850–900° C. In this case, the annealing process is performed in order to obtain a phase transformation of cobalt mono-silicide layers or titanium mono-silicide layers formed on the gate electrodes and source/drain regions of the MOS transistors as well as to densify the etch stop layer. The cobalt mono-silicide layer (or the titanium mono-silicide layer) exhibits a relatively high resistivity as compared to a cobalt di-silicide layer (or a titanium di-silicide layer). Thus, the annealing process is performed in order to convert the cobalt mono-silicide layers (or the titanium mono-silicide layers) into the cobalt di-silicide layers (or the titanium di-silicide layers).
However, if the above salicide technique corresponds to a nickel salicide technique, the annealing process performed at the high temperature of 850–900° C. increases electrical resistance of nickel silicide layers formed on gate electrodes and source/drain regions of MOS transistors. Accordingly, the characteristics of the MOS transistors are degraded.
Further, methods of fabricating a semiconductor device having low hydrogen content and low physical stress are taught in U.S. Pat. No. 6,071,784 to Mehta et al. According to Mehta et al., an etching stop layer is formed on a semiconductor substrate including MOS transistors. The etching stop layer is subjected to a heat treatment at a temperature of 725–775° C. to decrease hydrogen content therein. As a result, it is possible to stabilize the threshold characteristic of the MOS transistors. However, in the event that the MOS transistors are fabricated using a nickel salicide technique, the heat treatment of the etching stop layer causes phase transformation of nickel silicide layers formed by the nickel salicide technique. This is due to the high annealing temperature of 725–775° C. Thus, switching operations of the MOS transistors may be degraded.
In conclusion, methods of fabricating a MOS transistor using a nickel salicide technique should be carefully optimized.